module PC(clk,Addr,Reset,wt,Load,cout);
input clk;
input Load,Reset,wt; //Load:控制是否自动加一; Reset:清空; wt:控制是否从外部输入数字

input [7:0] Addr;        //外部输入8位地址
output reg[7:0] cout;   //输出地址到存储器

reg clk_pc; //分频后的时钟频率
reg [15:0] count; //分频计数


always @(posedge clk)
begin 
	if(count == 500)
	begin 
		count = 0;
		clk_pc = ~clk_pc;
	end 
	else 
		count = count + 1'b1;
end

always @(posedge clk_pc)
begin
	if(!Reset) //低电平清零
		cout=0;
	else
	begin
		if(wt) //
			cout=Addr;
		else
		begin
			if(Load)
				cout=cout+1'b1;
			else 
				cout=cout;
		end
	end
end

endmodule 